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(R)
TDA7502
IN-CAR REMOTE AMPLIFIER DSP
PRODUCT PREVIEW
24-Bit Fixed-point DSP core delivering up to 50 MIPS 2 x 512 x 24Bitof RAM forX andY datamemory. 1536 x 24 Bit of RAM for Program. 1536 x 24 Bit of Additional RAM memory usable for delay or program Serial Audio Interface. Debug Port. Control Interface for external GPIOs, Interrupts, and RESET. SPI and I2C for communication between external micro and DSP. Both master and slave operating modes. PLL Clock Oscillator 5V-tolerant 3V I/O interface DESCRIPTION This device is a high-performance, fully programmable DSP, suitable for a wide range of applications and particularly for Audio and Sound Processing. It contains a 24-bit 50 MIPS DSP core, several interfaces for control and data, plus a BLOCK DIAGRAM
SDI0 SDI1 SDI2 SDO0 SDO1 SDO2
TQFP44 (10 x 10)
configurable PLL. The computational power and the memory configuration make this device particularly suitable for in car equalisation. This device will offer the best trade-off between performance and cost when coupled with the TDA7531, or other devices of the same family. A library of sound processing functions is available for this device; some of these functions are: parametric equaliser, cross over filters, acoustic delay, dynamic compression, Vol/Bass/Treble/Fader, active equalisation, Stereo Spatial Enhancement.
VDD3 GND3
SCANEN TESTEN VDD4 GND4
LRCLKT SCKT LRCLKR SCKR SCL SDA
Serial Audio Interface I2C Interface
XAB XDB YAB YDB
512 x 24 X-RAM 512 x 24 Y-RAM 3072 x 24 P/Delay-RAM 128 x 24 BOOT-ROM
VDD5 GND5 VDD6 GND6
SS SCK MISO MOSI GPIO3 GPIO4 GPIO5 DBCK/GPIO1 DBIN/GPIO2
SPI Interface GPIO Debug interface
DBRQN/GPIO3 DBRQ
ORPHEUS 24bit DSP CORE
VDD1 GND1 VDD2 GND2
PAB PDB
RESET INT PVCC PGND
PLL oscillator
XTO XTI CLKOUT
April 1999
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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TDA7502
ABSOLUTE MAXIMUM RATINGS
Symbol VDDC V DDP VI, VIN Top Tstg Core DC Supply voltage Pads DC Supply voltage Digital or analog input voltage Operative temperature range Storage temperature range (plastic) Parameter Value 4.6 4.6 -0.5 to (VDDP +0.5) -40 to 85 -55 to 150 Unit V V V C C
PIN CONNECTION
GPIO5 GPIO4 GPIO3 GND6 VDD6 MISO MOSI SCK
36
SDA
35
VDD1 GND1 INT SCANEN TESTEN DBRQN DBOUT VDD2 GND2 DBCK DBIN
1 2 3 4 5 6 7 8 9 10
44 43
42
41
40 39
38
37
SS
SCL
34 33 32 31 30 29 28 27 26 25 24 23
SCKT LRCKT GND5 VDD5 SDO2 SDO1 SDO0 GND4 VDD4 SCKR LRCKR
11 12 13 14 15 16 17 18 19 20 21 22
CLKOUT
RESET
XTO XTI
PVCC
VDD3
PGND
GND3
SDI0
SDI1
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient Value 50 Unit C/W
PIN DESCRIPTION
N. 1 2 3 4 5 Name VDD1 GND1 INT SCANEN TESTEN Type I I I/O I I Reset Status (1) - 3.3V core supply. - - - - Core ground. External interrupt line (Input/Output). When this line is asserted low, the DSP may be interrupted. Acts as IRQA line of DSP core. SCAN Enable When active with TESTEN also active, controls the shifting of the internal scan chains. Test Enable. When active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting Debug Port Request Input. Means of entering the Debug mode of operation. Function
6
DBRQN
I
-
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SDI2
TDA7502
PIN DESCRIPTION (continued)
N. 7 8 9 10 Name DBOUT/GPIO2 VDD2 GND2 DBCK/GPIO0 Type I/O I I I/O Reset Status I - - I Function The serial data output for the Debug Port. Can also be used as a GPIO. 3.3V core supply. Core ground. Debug Port Bit Clock/Chip Status 1. The serial clock for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO Debug Port Serial Input/Chip Status 0. The serial data input for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO. Output Clock. PLL Clock Ground Input. Ground connection for oscillator circuit. PLL Clock Power Supply. Positive supply for PLL Clock Oscillator. Crystal Oscillator Output. Crystal Oscillator output drive. Crystal Oscillator Input. External Clock Input or crystal connection. System Reset. A logic low level applied to RESET input initializes DSPs. During Debug Mode if this pin is pulled low in while the DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will be reset. 3.3V Supply. Ground. SDI0 is a stereo digital audio data input pin channel 0. SDI1 is a stereo digital audio data input pin channel 1. SDI2 is a stereo digital audio data input pin channel 2. SAI receive bit clock. Master or slave. Left-Right clock for SAI Receiver. Master or slave. 3.3V Supply. Ground. SDO0 is a stereo digital audio data output pin channel 0. SDO1 is a stereo digital audio data output pin channel 1. SDO2 is a stereo digital audio data pin channel 2. 3.3V Supply. Ground. SAI transmit left/right clock. Master or slave. SAI transmit bit clock. Master or slave. Clock line for I2C bus. Schmitt trigger input. Data line for I2C bus. Schmitt trigger input. Bit clock for SPI control interface. Slave select input pin for SPI control interface. Serial Data Output for SPI type serial port when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Serial Data Input for SPI style serial port when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. 3.3V Supply. Ground. This pin is dedicated as general I/O. This pin is dedicated as general I/O. This pin is dedicated as general I/O.
11
DBIN/GPIO1
I/O
I
12 13 14 15 16 17
CLKOUT PGND PVCC XTO XTI RESET
O I I O I I/O
- - - High - I
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
VDD3 GND3 SDI0 SDI1 SDI2 SCKR LRCKR VDD4 GND4 SDO0 SDO1 SDO2 VDD5 GND5 LRCKT SCKT SCL SDA SCK SS MOSI MISO VDD6 GND6 GPIO3 GPIO4 GPIO5
I I I I I I/O I/O I I O O O GND I I/O I/O I/O I/O I I I/O I/O GND I I/O I/O I/O
- - - - - - - - - High High High - - - - - - - - I I - - - - -
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TDA7502
RECOMMENDED DC OPERATING CONDITIONS
Symbol VDDC Tj Parameter 3.3V Power Supply Voltage Operating Junction Temperature Test Condition Min. 3 -40 Typ. 3.3 Max. 3.6 125 Unit V C
POWER CONSUMPTION
Symbol Idd Parameter Maximum current for core power supply @3.3V Value 250 Unit mA
Note: 50MHz internal DSP clock at Tamb
FUNCTIONAL DESCRIPTION The TDA7502 contains one DSP Core and associated peripherals. 24-BIT DSP CORE. The DSP core is used to process the converted analog audio data coming from the CODEC chip via the SAI and return it for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP. Some capabilities of the DSPs are listed below: Single cycle multiply and accumulate with convergent rounding and condition code generation 2 x 56-bit Accumulators Double precision multiply Scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking 8 each of Address Registers, Address Offset Registers and Address Modulo Registers Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic Post-increment or decrement by 1 or by offset, Index by offset, predecrement address Repeat instruction and zero overhead DO loops Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations. Also Jump on bit test. 4 pin serial debug interface Debug access to all internal registers, buses
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and memory locations 5 word deep program address history FIFO Hardware and software breakpoints for both program and data memory accesses Debug Single stepping, Instruction injection and Disassembly of program memory DSP PERIPHERALS There are a number of peripherals that are tightly coupled to the DSP Core. Each of the peripherals are listed below and described in the following sections. 512 x 24-Bit X-RAM. 512 x 24-Bit Y-RAM. 3072 x 24-Bit Program RAM 128 x 24-Bit Boot ROM. Serial Audio Interface (SAI) Single Debug Port 2 Programmable Control Interface (SPI/I C) GPIO DATA AND PROGRAM MEMORY Each of the memories are described below. 512 x 24-Bit X-RAM (XRAM) This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from all peripheral blocks. 512 x 24 Bit Y-RAM (YRAM) This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data
TDA7502
ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from other blocks. 3072 X 24-Bit Program RAM This is a 3072 x 24-Bit Single Port SRAM used for storing and executing program code. The 16Bit PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding. Spare space in the Program area may be used as data memory to implement delay lines for example. 128 x 24-Bit Bootstrap ROM (PROM) This is a 128 x 24-Bit factory programmed Boot ROM used for storing the program sequence for initializing the DSP. Essentially this consists of a routine that is called when the DSP comes out of reset. There are three different boot modes supported by the boot ROM, one boots directly into PRAM, the second boots over the I2C bus and the third boots are the SPI bus. The boot mode is selected by the levels on GPIO3 and GPIO5 Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it can be returned through this interface. The features of the SAI are listed below. Three Synchronized Stereo Data Transmission Lines Three Synchronized Stereo Data Reception Lines Master/Slave operating modes Transmit and Receive Interrupt Logic triggers on Left/Right data pairs Receive and Transmit Data Registers have two locations to hold left and right data. simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. I C Interface The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus. Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. General Purpose Input/Output The DSP requires a set of external general purpose input/output lines, and a reset line. These signals are used by external devices to signal events to the DSP. The GPIO lines are implemented as DSP 's peripherals PLL Clock Oscillator The PLL Clock Oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (33 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 1 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update rate. The clocks to the DSP can be selected to be either the VCO output divided by 2 or 4 respectively, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting bit 1 of the PCON Register).
2
Serial Peripheral Interface The DSP core requires a serial interface to receive commands and data over the LAN. During an SPI transfer, data is transmitted and received
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TDA7502
Application Scheme The The TDA7502 IC will interface with an external processing. The TDA7502 then sends the nal CODEC chip (i.e. the TDA7531). The CODEC processed audio data back to the CODEC for D/A chip contains A/D converters that convert the conversion. A block diagram of the system is audio data and send it to the TDA7502 IC for sigshown in Fig. 1 below. Figure 1. Block Diagram of Car Amplifier Audio Sub-System.
.
To Microprocessor
EPROM (64Kx8)
Control Bus
TDA7502
6
TDA7531
Power Amplifier
Radio Inputs 4
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TDA7502
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.37 1.45 0.45 0.20 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 0.002 0.053 0.012 0.004 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.014 0.057 0.018 0.008 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E1
B
44 1 11
12
E
B
e
L
C
K
TQFP4410
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TDA7502
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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